The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 25 years, many of the advances in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.

The 26th edition will take place in Lausanne, Switzerland, from 29th August 2016 until 2nd September 2016. Tutorials and Workshops will run Monday and Friday while Tuesday through Thursday will take place the main conference.

Venue

The conference will be held on the EPFL campus in the brand-new Swiss Tech Convention Centre, a unique structure with a futuristic design. EPFL is one of the two Swiss Federal Institutes of Technology. With the status of a federal polytechnic university since 1969, the young engineering school has grown in many dimensions, to the extent of becoming a world renown institution of science and technology. EPFL is located in Lausanne in Switzerland, on the shores of the largest Alpine lake, Lake Geneva, and at the foot of the Alps, close to Mont Blanc. It is easy to reach by air through Geneva airport (more than 100 cities with non-stop flights, frequent comfortable direct trains from inside the airport to Lausanne in about 50 minutes) and through Zurich airport (connected non-stop to around 200 cities, frequent comfortable direct trains from inside the airport to Lausanne in about two hours and a half).

Programme

The conference programme will be published imminently but the tentative layout of the week-long programme is shown below. Please come back for more details!

Monday
29th Aug
Tuesday
30th Aug
Wednesday
31st Aug
Thursday
1st Sep
Friday
2nd Sep
 
morning Tutorials
and
Workshops
Main
Conference
Main
Conference
Main
Conference
Tutorials
and
Workshops
 
afternoon Tutorials
and
Workshops
Main
Conference
Main
Conference
Main
Conference
Tutorials
and
Workshops
 
  Social Event Demo Night
 
 

Tutorials & Workshops

The following tutorials and workshops will take place before and after the main conference.

Monday
29th Aug
  Friday
2nd Sep
morning   afternoon   morning   afternoon
 
Tutorial TM1
Embedded Design Using LabVIEW Real-Time and FPGA
Tutorial TF1
Embedded Systems and OpenCL on the Cyclone V SoC
 
Tutorial TM2
Hyperscale FPGA Research on Catapult
Tutorial TF2
Pynq for Zynq Devices
 
Tutorial TM3
Energy-efficient Acceleration for Neuro-inspired Computing On-a-Chip
Tutorial TM4
Practical on Benchmarking Real-Time and Energy Constrained 3D Robot Vision Applications with SLAMBench
Tutorial TF3
Accelerating Big Data Processing with Hadoop, Spark, and Memcached on Datacenters on Modern Clusters
 
Workshop WM1
FPGAs for Software Programmers (FSP 2016)
Workshop WF1
Soft Errors and Programmable Logic (SEPL 2016)
 
Workshop WF2
Security in Reconfigurable Devices: Challenges and Solutions (SecRec 2016)
Workshop WF3
Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers
 
morning   afternoon   morning   afternoon
Monday
29th Aug
  Friday
2nd Sep

Tutorial TM1
Embedded Design Using LabVIEW Real-Time and FPGA

Organizers: Jose Albuquerque Silva and Maha Moatemri (National Instruments, US)

Using high level synthesis (HLS) and an inherently parallel programming language, National Instruments (NI) provides software developers a powerful and efficient way to capture complex designs. This seminar explores the LabVIEW graphical embedded development tools and National Instruments off-the-shelf prototyping and deployment-ready systems. Discover first-hand how to design, prototype, and deploy real-time applications using NI LabVIEW Real-Time and FPGA programming tools and NI RIO hardware. Explore leading-edge control design tools and techniques to improve your design efficiency for custom systems and machines. Learn about closed loop control design, simulation, implementation, and monitoring including PID control and FPGA based machine analysis. During the workshop attendees will have also the opportunity to learn how to design real systems with NI myRIO and thus connecting the acquired knowledge with the teaching experience. NI myRIO is an embedded hardware device developed for teaching applications and designed for developing real, complex engineering systems using a dual-core ARM® CortexTM-A9 real-time processor and customized I/O with a Xilinx FPGA.

Tutorial TM2
Hyperscale FPGA Research on Catapult

Organizers: Andrew Putnam (Microsoft, US) and Derek Chiou (Microsoft and University of Texas Austin, US)

The Microsoft Catapult system is a multi-FPGA reconfigurable fabric designed for integration with modern hyperscale datacenters. Microsoft has donated two large systems for use by both academic and commercial researchers—one at EPFL, and one at TACC at the University of Texas (Austin). Similar hardware is available in very limited supply for individual systems. The goal of this donation is to facilitate large-scale, multi-FPGA research. This tutorial will introduce students to the Catapult hardware, software, and systems. Basic compilation of simple roles will be covered, as well as writing software to interact with those roles. We will also briefly cover the use of the EPFL and TACC systems, as well as any questions about promising research directions using the Catapult hardware.

Tutorial TM3
Energy-efficient Acceleration for Neuro-inspired Computing On-a-Chip

Organizers: Yu Cao, Jae-sun Seo, and Yu Wang (Arizona State University, US)

Neuro-inspired computing, has made enormous progress in recent years. Yet their performance on hardware is still limited by the scale of computation and the architecture of existing CPUs/GPUs. While special purpose hardware solutions help bring expensive algorithms to a low-power processor, limitations still exist in homogeneous architecture, memory footprint, communication, and online learning capability, especially for mobile/wearable systems with extreme power constraints. This tutorial will present our latest knowledge of hardware acceleration from multiple aspects. Examples include model/memory compression, data precision, architectural optimization, circuit operation, emerging devices, and neuromorphic motifs. These techniques will effectively reduce the computation complexity and improve the mapping of the algorithms to various hardware platforms.

For more details, please visit this website.

Tutorial TM4
Practical on Benchmarking Real-Time and Energy Constrained 3D Robot Vision Applications with SLAMBench

Organizers: Bruno Bodin, Luigi Nardi, and Harry Wagstaf (University of Edinburgh, UK)

During this tutorial we propose a practical on the robotics vision SLAMBench benchmarking framework. Simultaneous Localisation And Mapping (SLAM) systems aim to perform real-time localisation of the camera and 3D mapping “simultaneously” for a camera moving through an unknown environment. The SLAMBench benchmarking framework is a publicly-available software framework which represents a starting point for quantitative, comparable and validatable experimental research to investigate trade-offs in performance, accuracy and energy consumption of SLAM algorithms. Our goal is to ensure that attendees can install andrun the framework on their machine during the tutorial. No previous knowledge of computer vision is required. Invited speakers will talk about their experience with SLAMBench.

For more details, please visit this website.

Tutorial TF1
Embedded Systems and OpenCL on the Cyclone V SoC

Organizer: Kevin Nam (Altera, US)

The integration of a CPU and FPGA into an SoC allows the development of exciting applications that benefit from the strengths of each half. In this tutorial we will look at designing such applications using the Cyclone V SoC device. We will begin by examining the Cyclone V SoC device architecture, and writing baremetal code. We will then learn how to use a Linux environment to develop and run software programs that communicate with circuits placed inside the FPGA. Starting from the basics of running Linux on the Cyclone V SoC board, we will work our way up to designing a hardware-accelerated Linux application that offloads computation to a custom circuit placed in the FPGA. The tutorial will conclude with an introduction to the Altera OpenCL SDK, which provides a high-level design methodology for creating hardware-accelerated applications that use Altera FPGAs.

Tutorial TF2
Pynq for Zynq Devices

Organizers: Patrick Lysaght and Cathal McCabe (Xilinx, US)

Pynq is a new open-source framework for designing with Xilinx Zynq devices. Pynq enables programmers who design embedded systems to exploit the capabilities of Zynq APSoCs without having to use ASIC-style, CAD tools to design programmable logic circuits. Instead the APSoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed. The framework combines four main elements: (1) the use of a high-level productivity language, Python in this case; (2) Python-callable hardware libraries based on FPGA overlays; (3) a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors; and (4) Jupyter Notebook's client-side, web apps. The result is a web-centric programming environment that enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries. This tutorial will give a hands-on introduction to Pynq.

Tutorial TF3
Accelerating Big Data Processing with Hadoop, Spark, and Memcached on Datacenters on Modern Clusters

Organizers: DK Panda and Xioyi Lu (The Ohio State University, US)

Apache Hadoop and Spark are gaining prominence in handling Big Data and analytics. Similarly, Memcached in Web 2.0 environment is becoming important for large-scale query processing. These middleware are traditionally written with sockets and do not deliver best performance on datacenters with modern high performance networks. In this tutorial, we will provide an in-depth overview of the architecture of Hadoop components (HDFS, MapReduce, RPC, HBase, etc.), Spark and Memcached. We will examine the challenges in re-designing the networking and I/O components of these middleware with modern interconnects, protocols (such as InfiniBand, iWARP, RoCE, and RSocket) with RDMA and storage architecture. Using the publicly available software packages in the High-Performance Big Data (HiBD, http://hibd.cse.ohio-state.edu) project, we will provide case studies of the new designs for several Hadoop/Spark/Memcached components and their associated benefits. Through these case studies, we will also examine the interplay between high performance interconnects, storage systems (HDD and SSD), and multi-core platforms to achieve the best solutions for these components.

For more details, please visit this website.

Workshop WM1
FPGAs for Software Programmers (FSP 2016)

Organizers: Andreas Koch (Technische Universität Darmstadt, DE) and Markus Weinhardt (Hochschule Osnabrück, DE)
Proceedings Chair: Christian Hochberger (Technische Universität Darmstadt, DE)

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

For more details, please visit this website.

Workshop WF1
Soft Errors and Programmable Logic (SEPL 2016)

Organizers: Mike Wirthlin (Brigham Young University, US) and Mike Hutton (Altera, US)

Programmable devices are very attractive for a variety of applications due to their high levels of logic integration, their flexibility during the project lifetime, and their reconfigurability. However, SRAM-based FPGAs are particularly susceptible to single-event upsets due to ionizing radiation found in the terrestrial environment, high-altitude applications, space, and unique radiation environments such as high-energy physics. The objective of this workshop is to share information and results related to the reliable use of SRAM-based FPGAs in the presence of single-event effects. This topic is of interest to users of FPGAs in a variety of unique environments such as space, avionics, high-reliability, FPGA-based data centers, and high-energy physics. This topic will be of increasing interest to a variety of users as the densities of FPGAs continue to increase and the effects of ionizing radiation play a more important part of large FPGA-based systems.

For more details, please visit this website.

Workshop WF2
Security in Reconfigurable Devices: Challenges and Solutions (SecRec 2016)

Organizers: Lejla Batina (Radboud University, NL), Francesco Regazzoni (USI, CH), Ricardo Chaves (INESC-ID, PT), Nele Mentens (KU Leuven, BE), and Tim Güneysu (University of Bremen, DE)

Reconfigurable systems are used to control critical application or to handle sensitive information. To safely and reliably implement such systems, it is of paramount importance that designers have a complete awareness of the risks to be avoided, the main security threats, and the most advanced protection available. Similar to other digital circuits, designs implemented using FPGAs are susceptible to physical attacks and to hardware Trojans. Nevertheless, FPGAs offer new and unique possibilities for implementing secure features, including quantum resistant algorithms, and for guaranteeing robustness against reverse engineering. The SecRec Workshop aims to bring researchers and experts together to discuss current and future research directions regarding threats, attacks, design methodologies, and basic blocks currently used to address security problems using reconfigurable hardware.

For more details, please visit this website.

Workshop WF3
Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers

Organizers: Mario Porrmann (Bielefeld University, DE), Zain Ul‐Abdin (Halmstad University, SE), and Madhura Purnaprajna (Amrita University, IN)

Reconfigurable computing platforms, which offer massive parallelism coupled with the capability of run‐time adaptation to changing application requirements are becoming core components of the information processing in embedded systems with high computational demand but limited energy budget. In parallel to their utilization for IoT devices and in cyber physical systems, reconfigurable systems are used together with GPGPUs in data centres for high performance and cloud computing. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for a wide range of applications. Partial reconfiguration—a research topic for two decades—is becoming mainstream for embedded systems and is seen as an important requirement for efficient utilization in HPC and cloud computing. However, developing systems and applications that employ such architectures still poses many challenges, which are currently tackled in several research projects. In this workshop, we want to bring together researchers from a wide variety of international projects to share their achievements and innovations in the area of reconfigurable computing, ranging from embedded systems to reconfigurable hyperscale servers. The workshop will provide a platform for open discussion of ongoing research with interested attendees from industry and academia.

For more details, please visit this website.

Registration

To register for the conference and for all tutorials workshops, please visit the registration site. After registration, you will receive by e-mail a personal link that can be used to update your registration at any time (e.g., to participate in tutorials or to add tickets for the social event). If you are unable to pay by credit card because of exceptional circumstances, please register as usual (but leaving the billing info blank) and contact the Registration Chair. Please note that registrations are not refundable.

Early registration ends at midnight AoE on 15th July 2016. Online registration will close at midnight AoE on 22nd August 2016. On-site registration will be available at the Late Registration rates and only by credit card or PayPal.

Early
(before 15th July)
Late
(from 16th July)
Main conference
(full registration)
625 CHF 825 CHF
Main conference
(students)
335 CHF 425 CHF
Any tutorials or workshops
on Monday
60 CHF/day
(if registered for the main conference)
125 CHF/day
(otherwise)
Any tutorials or workshops
on Friday
60 CHF/day
(if registered for the main conference)
125 CHF/day
(otherwise)
Additional tickets
for the social event
120 CHF
Additional pages
(max 2, full papers only)
150 CHF

Accommodation

A number of rooms have been reserved for the conference in various hotels. They will be kept available for the FPL'16 participants on a first-come first-served basis until a date specified by the hotel (usually between end of June and early August). Below is the offering by these hotels; to book a reserved room in any of these hotels, you should e-mail directly the hotel (envelope link in the table) and mention "FPL16" as a reference to the reservation. Note that at the time of this writing some of these hotels already look fully booked on common travel websites. Please also note that the reservation is only a courtesy by the hotels to our participants.

Hotel Book by Offer Breakfast
Alpha-Palmiers
★★★★
5% discount if booked directly
Continental
★★★★
27th July Single: 175 CHF
Double (1 p.): 220 CHF
Double (2 pp.): 280 CHF
incl.
Starling
★★★★
26th July Double (1 p.): 160 CHF
Double (2 pp.): 195 CHF
incl.
Victoria
★★★★
27th July Single: 192 CHF
Double (1 p.): 222 CHF
incl.
46a
★★★
28th June Studio (1 p.): 145 CHF
Studio (2 pp.): 160 CHF
incl.
Aulac
★★★
10th August Single: 145 CHF
Large single: 160 CHF
Double: 190 CHF
incl.
Crystal
★★★
29th July Single: 131 CHF
Double (1 p.): 161 CHF
Double (2 pp.): 181 CHF
incl.
Du Port
★★★
8th August Single (town side): 145 CHF
Double (2 pp., lake side): 195 CHF
Double (2 pp., town side): 175 CHF
incl.
LHOTEL
★★★
30th June Single: 102.50 CHF
Double (2 pp.): 142.50 CHF
14 CHF
SwissTech
★★★
15th July Single: 120 CHF 11 CHF
Ibis
★★
13th August Double (1 p., 28/08): 126 CHF
Double (1 p., 29/08 and 01/09): 155 CHF
Double (1 p., 30/08 and 31/08): 161 CHF
no
Jeunotel
(Youth Hostel)
30th June Single: 87 CHF
Double: 59 CHF/person
Quadruple: 40 CHF/person
no

For your convenience, the map below indicates the location of all of the above hotels together with the main sites of the conference and some touristic landmarks. Note that the SwissTech Hotel is right on the side of the SwissTech Convention Centre and literally on the platform of the metro connecting EPFL with the city centre. Most of the rooms have been reserved there.

Local Transportation

The best means to reach Lausanne from all Swiss airports is train. You can find the most convenient connections from the CFF website or using Google Maps. Both Geneva and Zurich airports have a train station inside the building and direct trains to Lausanne. You should typically take one-way tickets (return tickets are valid only for the same day) and get regular tickets (most Swiss residents have a 1/2-price card). A second class regular ticket to/from Geneva Airport costs 27 CHF and one to/from Zurich Airport costs 77 CHF. Second class is quite confortable; first class, depending on the route and times may have the advantage of more free seats available (but not always!).

Public transportation in Lausanne is fairly well developed and efficient. You can find the most convenient connections and all timetables from the TL website or, again, using Google Maps. In particular, you can find on the TL website the network map in PDF. To reach EPFL and STCC, the most convenient line is m1, a metro line, and the stop you want is named, unimaginatively, EPFL. STCC is immediately recognizable from the m1 stop. Note that you could take m1 to EPFL both from the city centre (stop Lausanne-Flon) as well as from the Renens train station (on the Geneva – Lausanne line, but few trains from the airport stop there). Finally, everyone staying in a hotel in Lausanne will receive a free daily ticket, so you should not be concerned by how to obtain tickets.

The use of private cars to come to Lausanne is usually not a recommended option, unless the hotel offers parking spaces (free and unlimited street parking is almost inexistent in the city centre). Coming to EPFL by private car is also not very convenient: there is no public parking at STCC and parking at EPFL requires you to purchase daily parking passes at the central information desk. Please consider that public transportation is much more convenient.

Finally, if you need to find a place at EPFL, you may find useful the interactive map of EPFL

Tourism

Late summer is a great time to visit the region of Lake Geneva and Switzerland. There are many websites with abundant information on Lausanne and Switzerland.


The official Lausanne tourism website.


The official Lake Geneva Region tourism website.


The official Switzerland tourism website.


The official Gran Tour of Switzerland website.


And there is a City Guide Lausanne app available for both Android and iOS.

Important Dates

Abstract submission deadline: 20th March 2016

Paper submission deadline: 27th March 2016 AoE (please note: no extensions!)

Demo night, PhD forum, tutorials, and workshops submission deadline: 8th May 2016

Notifications: around 15th June 2016

Final manuscripts deadline: 3rd July 2016

Early registration deadline: 15th July 2016

Online registration deadline: 22nd August 2016

Calls for Contributions

Here is the final Call for Contributions in PDF.

Here is the final Call for PhD Forum and Demo Night Contributions in PDF.

The conference proceedings will me made available online at the FPL 2016 venue and will be published through IEEE Xplore after the conference.

Submissions

Authors are required to use the standard IEEE templates in format A4 and not to include page numbers, to ensure compatibility with IEEE Xplore. Templates for LaTeX and Microsoft Word 2003 are available directly from IEEE.

FPL 2016 uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. Exceptions may be allowed with prior approval of the Programme Chairs, in cases where the authors’ identity is vital to evaluating the paper (e.g., papers presenting updates of infrastructure used by the FPGA community). References to the authors’ prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as "Removed for blind review", but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission.

Papers can be submitted for one of the following categories (please note the later deadline for the last two types of papers). All papers will be published in the proceedings and will appear in IEEE Xplore. Strict paper length limitations are as follows:

Full papers 8 pages + up to 2 additional pages which can be purchased at the time of registration for 150 CHF/page + references (i.e., references are not counted in the page budget)
Short papers 4 pages, including references
PhD Forum papers 2 pages, including references
Demo Night papers 1-page abstract, including references

Use this submission site to submit your paper. Please note that the submission of the full- and short-paper abstracts by the relevant deadline is mandatory and that deadlines are not going to be extended.

Organizing Committee

General Chairs

  • Paolo Ienne, EPFL, CH
  • Walid Najjar, University of California Riverside, US

Programme Chairs

  • Jason Anderson, University of Toronto, CA
  • Philip Brisk, University of California Riverside, US

Tutorial and Workshop Chairs

  • Pierre‐Emmanuel Gaillardon, University of Utah, US
  • Michael Hübner, Ruhr-Universität Bochum, DE

PhD Forum and Demo Night Chairs

  • Mirjana Stojilović, HEIG‐VD, CH
  • Yann Thoma, HEIG‐VD, CH

Proceedings Chair

  • Walter Stechele, TU München, DE

Publicity Chair

  • Kubilay Atasu, IBM Research – Zurich, CH

Local Arrangements Chair

  • Chantal Schneeberger, EPFL, CH

Local Arrangements Team

  • Mikhail Asiatici, EPFL, CH
  • Andrew Becker, EPFL, CH
  • Lana Josipović, EPFL, CH
  • Ana Petkovska, EPFL, CH
  • Grace Zgheib, EPFL, CH

Registration Chair

  • Andrew Becker, EPFL, CH

Programme Committee

  • Michael Adler, Intel, US
  • Hideharu Amano, Keio University, JP
  • David Andrews, University of Arkansas, US
  • Sameh Asaad, IBM, US
  • Kubilay Atasu, IBM, CH
  • Peter Athanas, Virginia Tech, US
  • Trevor Bauer, Xilinx, US
  • Samuel Bayliss, Xilinx, US
  • Kia Bazargan, University of Minnesota, US
  • Jürgen Becker, Karlsruher Institut für Technologie, DE
  • Tobias Becker, Maxeler Technologies, UK
  • Pascal Benoit, Université Montpellier 2, FR
  • Neil Bergmann, University of Queensland, AU
  • Koen Bertels, Technische Universiteit Delft, NL
  • Vaughn Betz, University of Toronto, CA
  • Dustyn Blasig, National Instruments, US
  • Michaela Blott, Xilinx, IE
  • Christophe Bobda, University of Arkansas, US
  • Cristiana Bolchini, Politecnico di Milano, IT
  • Christos Bouganis, Imperial College London, UK
  • Eli Bozorgzadeh, University of California Irvine, US
  • Gordon Brebner, Xilinx, US
  • Stephen Brown, Altera, CA
  • João M. P. Cardoso, Universidade do Porto, PT
  • Benjamin Carrion Schafer, Hong Kong Polytechnic University, HK
  • Luigi Carro, Universidade Federal do Rio Grande do Sul, BR
  • Deming Chen, University of Illinois at Urbana-Champaign, US
  • Peter Cheung, Imperial College London, UK
  • Kiyoung Choi, Seoul National University, KR
  • Paul Chow, University of Toronto, CA
  • Jason Cong, University of California Los Angeles, US
  • Philippe Coussy, Université de Bretagne Sud, FR
  • Jose Gabriel Coutinho, Imperial College London, UK
  • Rene Cumplido, Instituto Nacional de Astrofisica, MX
  • Martin Danek, Daiteq, CZ
  • Anup Das, University of Southampton, UK
  • Sabya Das, Xilinx, US
  • Eduardo de la Torre, Universidad Politécnica de Madrid, ES
  • André DeHon, University of Pennsylvania, US
  • Steven Derrien, Université de Rennes 1, FR
  • Oliver Diessel, University of New South Wales, AU
  • Pedro Diniz, University of Southern California, US
  • Apostolos Dollas, Technical University of Crete, GR
  • Carl Ebeling, Altera, US
  • Suhaib A. Fahmy, University of Warwick, UK
  • Fabrizio Ferrandi, Politecnico di Milano, IT
  • Elliott Fleming, Intel, US
  • Blair Fort, University of Toronto, CA
  • Roberto Giorgi, Università di Siena, IT
  • Diana Goehringer, Ruhr-Universität Bochum, DE
  • Guy Gogniat, Université de Bretagne Sud, FR
  • Maya Gokhale, Lawrence Livermore National Laboratory, US
  • Kees Goossens, Technische Universiteit Eindhoven, NL
  • Ann Gordon-Ross, University of Florida, US
  • David Greaves, University of Cambridge, UK
  • Jonathan Greene, Microsemi, US
  • Yajun Ha, National University of Singapore, SG
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP
  • Reiner Hartenstein, Technische Universität Kaiserslautern, DE
  • Martin Herbordt, Boston University, US
  • James C. Hoe, Carnegie Mellon University, US
  • Michael Hübner, Ruhr-Universität Bochum, DE
  • Miaoqing Huang, University of Arkansas, US
  • Eddie Hung, Imperial College London, UK
  • Paolo Ienne, EPFL, CH
  • Arpith Jacob, IBM, US
  • Nachiket Kapre, Nanyang Technological University, SG
  • Sinan Kaptanoglu, Microsemi, US
  • Wolfgang Karl, Karlsruher Institut für Technologie, DE
  • Ryan Kastner, University of California San Diego, US
  • Alireza Kaviani, Xilinx, US
  • Tom Kean, Algotronix, UK
  • Udo Kebschull, Goethe Universität Frankfurt, DE
  • Andrew Kennings, University of Waterloo, CA
  • Kenneth Kent, University of New Brunswick, CA
  • Taemin Kim, Intel, US
  • Kenji Kise, Tokyo Institute of Technology, JP
  • Vipin Kizheppatt, Mahindra École Centrale, IN
  • Andreas Koch, Technische Universität Darmstadt, DE
  • Dirk Koch, University of Manchester, UK
  • Jan Korenek, Brno University of Technology, CZ
  • Akash Kumar, Technische Universität Dresden, DE
  • Martin Langhammer, Altera, UK
  • Luciano Lavagno, Politecnico di Torino, IT
  • Miriam Leeser, Northeastern University, US
  • Guy Lemieux, University of British Columbia, CA
  • Philip Leong, University of Sydney, AU
  • Wayne Luk, Imperial College London, UK
  • Patrick Lysaght, Xilinx, US
  • Wai-Kei Mak, National Tsing Hua University, TW
  • Tsutomu Maruyama, University of Tsukuba, JP
  • Cathal McCabe, Xilinx, IE
  • Nele Mentens, Katholieke Universiteit Leuven, BE
  • Antonio Miele, Politecnico di Milano, IT
  • Roger Moussalli, IBM, US
  • Walid Najjar, University of California Riverside, US
  • Brent Nelson, Brigham Young University, US
  • Smail Niar, Université de Valenciennes, FR
  • David Novo, Université Montpellier 2, FR
  • Jose Nunez-Yanez, University of Bristol, UK
  • Gianluca Palermo, Politecnico di Milano, IT
  • Ioannis Papaefstathiou, Technical University of Crete, GR
  • Cameron Patterson, Virginia Tech, US
  • Christian Pilato, Columbia University, US
  • Thilo Pionteck, Universität zu Lübeck, DE
  • Marco Platzner, Universität Paderborn, DE
  • Christian Plessl, Universität Paderborn, DE
  • Dionisios Pnevmatikatos, Technical University of Crete, GR
  • Daniel Poznanovic, Cray, US
  • Madhura Purnaprajna, Amrita University, IN
  • Rodric Rabbah, IBM, US
  • Kyle Rupnow, Advanced Digital Sciences Center, SG
  • Mazen Saghir, American University of Beirut, LB
  • Kentaro Sano, Tohoku University, JP
  • Marco D. Santambrogio, Politecnico di Milano, IT
  • Paul Schumacher, Xilinx, US
  • Olivier Sentieys, Université de Rennes 1, FR
  • Muhammad Shafique, Karlsruher Institut für Technologie, DE
  • Lesley Shannon, Simon Fraser University, CA
  • Cristina Silvano, Politecnico di Milano, IT
  • Nicolas Sklavos, University of Patras, GR
  • Ioannis Sourdis, Chalmers Tekniska Högskola, SE
  • Dirk Stroobandt, Universiteit Gent, BE
  • Henry Styles, Xilinx, US
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
  • Russ Tessier, University of Massachusetts Amherst, US
  • David Thomas, Imperial College London, UK
  • Tim Todman, Imperial College London, UK
  • Hiroyuki Tomiyama, Ritsumeikan University, JP
  • Lionel Torres, Université Montpellier 2, FR
  • Jim Tørresen, Universitetet i Oslo, NO
  • Steve Trimberger, Xilinx, US
  • Wim Vanderbauwhede, University of Glasgow, UK
  • Tanya Vladimirova, University of Leicester, UK
  • Qiang Wang, Huawei, US
  • John Wawrzynek, University of California Berkeley, US
  • Norbert Wehn, Universität Kaiserslautern, DE
  • Markus Weinhardt, Hochschule Osnabrück, DE
  • Gabriel Weisz, Information Sciences Institute, US
  • Steve Wilton, University of British Columbia, CA
  • Michael Wirthlin, Brigham Young University, US
  • Stephan Wong, Technische Universiteit Delft, NL
  • Roger Woods, Queen's University Belfast, UK
  • Sotirios Xydis, National Technical University of Athens, GR
  • Yoshiki Yamaguchi, University of Tsukuba, JP
  • Wei Zhang, Hong Kong University of Science and Technology, HK
  • Zhiru Zhang, Cornell University, US
  • Daniel Ziener, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
  • Peter Zipf, Universität Kassel, DE

Steering Committee

Chairman

  • Patrick Lysaght, Xilinx, US
  • Jürgen Becker, Karlsruher Institut für Technologie, DE
  • Koen Bertels, Technische Universiteit Delft, NL
  • Eduardo Boemo, Universidad Autónoma de Madrid, ES
  • João M. P. Cardoso, Universidade do Porto, PT
  • Peter Y. K. Cheung, Imperial College London, UK
  • Martin Danek, Daiteq, CZ
  • Apostolos Dollas, Technical University of Crete, GR
  • Fabrizio Ferrandi, Politecnico di Milano, IT
  • Manfred Glesner, Technische Universität Darmstadt, DE
  • John Gray, consultant, UK
  • Reiner Hartenstein, Technische Universität Kaiserslautern, DE
  • Andreas Herkersdorf, Technische Universität München, DE
  • Udo Kebschull, Goethe Universität Frankfurt, DE
  • Wayne Luk, Imperial College London, UK
  • Jari Nurmi, Tampere University of Technology, FI
  • Lionel Torres, Université Montpellier 2, FR
  • Jim Tørresen, Universitetet i Oslo, NO

Sponsors

Technical Sponsor

  • IEEE

Platinum Level

  • EcoCloud
  • Huawei

Golden Level

  • Altera
  • Micron
  • Xilinx

Silver Level

  • Algo-Logic
  • Atomic Rules
  • IBM

Previous Editions

  • FPL 2015: London, UK
  • FPL 2014: Munich, DE
  • FPL 2013: Porto, PT
  • FPL 2012: Oslo, NO
  • FPL 2011: Chania, GR
  • FPL 2010: Milano, IT
  • FPL 2009: Prague, CZ
  • FPL 2008: Heidelberg, DE
  • FPL 2007: Amsterdam, NL
  • FPL 2006: Madrid, ES
  • FPL 2005: Tampere, FI
  • FPL 2004: Leuven, BE
  • FPL 2003: Lisbon, PT
  • FPL 2002: La Grande-Motte, FR
  • FPL 2001: Belfast, UK
  • FPL 2000: Villach, AT
  • FPL 1999: Glasgow, UK
  • FPL 1998: Tallinn, EE
  • FPL 1997: London, UK
  • FPL 1996: Darmstadt, DE
  • FPL 1995: Oxford, UK
  • FPL 1994: Prague, CZ
  • FPL 1993: Oxford, UK
  • FPL 1992: Vienna, AT
  • FPL 1991: Oxford, UK